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R8A66160DD/SP
16-BIT LED DRIVER WITH SHIFT REGISTER AND LATCH
REJ03F0261-0100 Rev. 1.00 Jan.10. 2008
DESCRIPTION
R8A66160 is a LED array driver having a 16-bit serial input and parallel output shift register function with direct coupled reset input and output latch function. This product guarantees the output current of 24mA (Vcc =5V case) which is sufficient for cathode common LED drive, capable of following 16-bits continuously at the same time. Parallel output is open drain output. In addition, as this product has been designed in complete CMOS, power consumption can be greatly reduced when compared with conventional BIPOLAR or Bi-CMOS products. Furthermore, pin layout ensures the realization of an easy printed circuit. R8A66160 is the succession product of M66310.
FEATURES
Cathode common LED drive VCC 5V or 3.3V single power supply High output current: all parallel outputs QA~QP IOH=-24mA (at VCC =5.0V) IOH=-12mA (at VCC =3.3V) simultaneous lighting available Low power dissipation: 100uW/package (max) (Vcc=5.0V, Ta=25oC, quiescent state) High noise margin: Schmitt input circuit provides responsiveness to a long line length Equipped with direct-coupled reset Open drain output: (except serial data output SQP) Wide operating temperature range: Ta=-40oC~+85oC Pin layout facilitates printed circuit wiring. (This layout facilitates cascade connection and LED connection)
APPLICATION
LED array drive, The various LED display modules PPC, Printer, VCR, Mini-compo, Button-Telephone etc. All of LED display equipment
BLOCK DIAGRAM
LOGIC DIAGRAM
QA
1 PARALLEL DATA OUTPUTS SERIAL DATA OUTPUT
QB
2
QC
24
QD
23
QE
22
QF
21
QG
20
QH
19
QI
18
QJ
17
QK
16
QL
15
QM
14
QN
13
QO
11
QP
12
SQP
10
Vcc
3
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
Q CK DR
S
S
S
S
5
4
OE
A
DATA signal OE signal
ENABLE SERIAL INPUT DATA INPUT
PARALLEL DATA OUTPUTS QA QP OUTPUT FORMAT
SERIAL DATA OUTPUT SQP
8
7
6
S
9
CKS
R
CKL GND
SHIFT DIRECT LATCH CLOCK RESET CLOCK INPUT INPUT INPUT
REJ03F0261-0100 Rev.1.00 Jan.10.2008 page 1 of 7
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R8A66160DD/SP
PIN CONFIGURATION ( TOP VIEW )
QA QB VCC SERIAL DATA INPUT ENABLE INPUT LATCH CLOCK INPUT DIRECT RESET INPUT SHIFT CLOCK INPUT A OE CKL R CKS GND SERIAL DATA OUTPUT PARALLEL DATA OUTPUTS SQP QO QP
1 2 3 4 5 6 7 8 9 10 11 12 SQP QO QP A OE CKL R CKS QA QB QC QD QE QF QG QH QI QJ QK QL QM QN 24 23 22 21 20 19 18 17 16 15 14 13
PARALLEL DATA OUTPUTS
QC QD QE QF QG QH QI QJ QK QL QM QN PARALLEL DATA OUTPUTS
FUNCTIONAL DESCRIPTION
As R8A66160 uses silicon gate CMOS process. It realizes high-speed and high-output currents sufficient for LED drive while maintaining low power consumption and allowance for high noises. Each bit of a shift register consists of two flip-flop having independent clocks for shifting and latching. As for clock input, shift clock input CKS and latch clock input CKL are independent from each other, shift and latch operations being made when "L" changes to "H". Serial data input A is the data input of the first-step shift register and the signal of A shifts shifting registers one by one when a pulse is impressed to CKS. When A is "L", the signal of "L" shifts. When the pulse is impressed to CKL, the contents of the shifting register at that time are stored in a latching register, and they appear in the parallel data outputs from QA ~ QP. Outputs QA ~ QP are open drain outputs. To extend the number of bits, use the serial data output SQP which shows the output of the shifting register of the 16th bit. When reset input R is changed to "L", QA ~ QP and SQP are reset. In this case, shifting and latching register are reset. If "H" is impressed to output enable input OE, QA ~ QP reaches the high impedance state, but SQP does not reach the high impedance state. Furthermore, change in OE does not affect shift operation.
FUNCTION TABLE (Note: 1)
Operation mode Reset Shift t1
Shift Latch t2 Latch operation Shift t1
Input R CKS CKL L XX H H H H X X X X X X X A X H X L X X OE X L L L L H QA Z QA H QA Z Z
0
Parallel data output QB QC QD Z Z Z QE Z QF Z QG QH Z Z QI Z QJ Z QK QL QM Z Z Z QN QO Z Z
QP SQP ZL
Serial data Remarks output
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QB QC QD QE QF QG QH QI QJ QK QL QM QN QO QP qO0 0 qB0 qC0 qD0 qE0 qF0 qG0 qH0 qI 0 qJ 0 qK0 qL 0 qM0 qN0 qO0 qO0 qA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QB QC QD QE QF QG QH QI QJ QK QL QM QN QO QP qO0 0 qB0 qC0 qD0 qE0 qF0 qG0 qH0 qI 0 qJ 0 qK0 qL 0 qM0 qN0 qO0 qO0 qA
Output lighting "H" Output lights-out "L"
0
Latch t2 Output disable Note1: Q X q0 q t1, t2 Z
0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
qP
Change from low-level to high-level Output state Q before CKL changed Irrelevant Contents of shift register before CKS changed Contents of shift register t2 is set after t1 is set High Impedance
REJ03F0261-0100 Rev.1.00 Jan.10.2008 page 2 of 7
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R8A66160DD/SP
ABSOLUTE MAXIMUM RATINGS (Ta=-40~+85 C, unless otherwise noted)
Symbol VCC VI VO IO Parameter Supply voltage Input voltage Output voltage Output current per output pin QA ~ QP SQP Conditions Ratings -0.5 ~ +7.0 -0.5 ~ VCC+0.5 -0.5 ~ VCC+0.5 -50 25 -410, +20 500 -65 ~+150 Unit V V V mA mA mW o C
o
ICC Supply / GND current VCC, GND Pd Power dissipation (Note 2) Tstg Storage temperature range Note 2: R8A66160SP; Ta=-40~+70oC, Ta=+70~+85oC are derated at -6mW/oC.
RECOMMENDED OPERATING CONDITIONS (Ta=-40~+85 C, unless otherwise noted)
Symbol VCC VI VO Topr Supply voltage Input voltage Output voltage Operating temperature range Parameter 5.0V support 3.3V support Min. 4.5 3.0 0 0 -40 Limits Typ. 5.0 3.3 Max. 5.5 3.6 VCC VCC +85 Unit V V V V o C
o
REJ03F0261-0100 Rev.1.00 Jan.10.2008 page 3 of 7
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R8A66160DD/SP
ELECTRICAL CHARACTERISTICS 5.0V version support specifications (Ta=-40~+85 C,Vcc=4.5V~5.5V, unless otherwise noted)
o
Symbol VT+ VT-
Parameter Positive-going threshold voltage Negative-going threshold voltage High-level output voltage High-level output voltage Low-level output voltage QA ~ QP
Test conditions VO=0.1V, VCC-0.1V |IO|=20uA VO=0.1V, VCC-0.1V |IO|=20uA IOH= -20uA VI=VT+,VTVCC=4.5V IOH= -24mA (Note3) IOH= -40mA IOH= -20uA IOH= -4mA IOL= 20uA IOL= 4mA VI=VT+,VTVCC=4.5V VI=VT+,VTVCC=4.5V
Min. 0.35xVCC 0.20xVCC VCC-0.1 3.66 3.25 VCC-0.1 3.66
Limits Typ.
Max. 0.70xVCC 0.55xVCC
Unit V V
VOH
V
VOH VOL IIH IIL IO
SQP SQP
V 0.10 0.53 5 -5 10 -10 V uA uA uA
High-level input current Low-level input current Maximum output leakage current QA ~ QP
VI=VCC, VCC=5.5V VI=GND, VCC=5.5V VI=VT+,VTVCC=5.5V VO=VCC VO=GND
ICC Quiescent supply current VI=VCC,GND, VCC=5.5V 200 uA Note 3: R8A66160 is used under the condition of an output current IOH=-40mA, the number of simultaneous drive outputs is restricted as shown in the Duty Cycle - IOH of TYPICAL CHARACTERISTICS.
3.3V version support specifications (Ta=-40~+85 C,Vcc=3.0V~3.6V, unless otherwise noted)
o
Symbol VT+ VT-
Parameter Positive-going threshold voltage Negative-going threshold voltage High-level output voltage High-level output voltage Low-level output voltage QA ~ QP
Test conditions VO=0.1V, VCC-0.1V |IO|=20uA VO=0.1V, VCC-0.1V |IO|=20uA IOH= -20uA VI=VT+,VTIOH= -12mA VCC=3.0V IOH= -20mA VI=VT+,VTVCC=3.0V VI=VT+,VTVCC=3.0V IOH= -20uA IOH= -2mA IOL= 20uA IOL= 2mA
Min. 0.35xVCC 0.20xVCC VCC-0.1 2.34 2.08 VCC-0.1 2.60
Limits Typ.
Max. 0.70xVCC 0.55xVCC
Unit V V
VOH
V
VOH VOL IIH IIL IO ICC
SQP SQP
V 0.10 0.40 5 -5 10 -10 200 V uA uA uA uA
High-level input current Low-level input current Maximum output leakage current QA ~ QP
VI=VCC, VCC=3.6V VI=GND, VCC=3.6V VI=VT+,VTVCC=3.6V VO=VCC VO=GND
Quiescent supply current
VI=VCC,GND, VCC=3.6V
REJ03F0261-0100 Rev.1.00 Jan.10.2008 page 4 of 7
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R8A66160DD/SP
SWITCHING CHARACTERISTICS (Ta=-40~+85 C,Vcc=5.0V or 3.3V)
Symbol fmax tPLH tPHL tPHL tPHZ tPZH tPHZ tPZH tPHZ CI Parameter Maximum clock frequency Output "L"-"H" and "H"-"L" propagation time Output "H"-"L" propagation time Output "H"-"Z" propagation time Output "Z"-"H" propagation time Output "H"-"Z" propagation time Output "Z"-"H" propagation time Output "H"-"Z" propagation time Input capacitance Test conditions CKS - SQP R - SQP R - QA ~ QP (turned off) CKL - QA ~ QP (turned on) CKL - QA ~ QP (turned off) OE - QA ~ QP (turned on) OE - QA ~ QP (turned off) 5.0V specification Min. Typ. Max. 4 125 125 125 CL=50pF RL=1K (Note 4) 200 125 200 125 200 10 3.3V specification Min. Typ. Max. 3.3 150 150 150 220 150 220 150 220 10 Unit MHz ns ns ns ns ns ns ns ns pF
o
TIMING REQUIREMENTS (Ta=-40~+85 C,Vcc=5.0V or 3.3V)
Symbol tw tsu tsu th trec Parameter CKS, CKL, R pulse width A setup time with respect to CKS CKS setup time with respect to CKL A hold time with respect to CKS R recovery time with respect to CKS, CKL (Note 4) Test conditions 5.0V specification Min. Typ. Max. 125 125 125 15 70 3.3V specification Min. Typ. Max. 150 150 150 20 80 Unit ns ns ns ns ns
o
Note4 : Test Circuit
INPUT VCC
PG 50
DUT SQP GND CL CL RL
QA
QP
(1) The pulse generator (PG) has the following characteristics (10%~90%) : tr=6ns,tf=6ns (2) The capacitance CL includes stray wiring capacitance and the probe input capacitance.
REJ03F0261-0100 Rev.1.00 Jan.10.2008 page 5 of 7
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R8A66160DD/SP
TYPICAL CHARACTERISTICS
Repetition frequency 10Hz Numbers in indicate the number of output circuits that operate simultaneously. Current values are per circuit.
Duty Cycle-IOH Characteristics Duty Cycle-IOH Characteristics
From top to bottom
Vcc=4.5V, Ta 25
Vcc=4.5V, Ta
85
0 Duty Cycle (%)
20
40
60
80
100
Duty Cycle (%)
TIMING DIAGRAM
tw
VCC CKS
50% tPLH 50% 50% tPHL 50%
VCC CKL
50%
GND
tPZH
GND VOH
50% tPHZ
SQP
VOH
50%
VOL
QA
QP
tw
VCC R
50% 50% trec
QA
QP
90%
VOH
GND VCC
50%
CKS
tPHL
VCC GND VOH A
50% tsu th 50% 50%
GND VCC GND
SQP
tPHZ
50%
VOL
90%
CKS
VOH
QA
QP
VCC OE
50% tPZH 50% tPHZ 50% 90%
VCC CKS
50% tsu tw
GND VOH CKL
GND VCC
50% 50%
QA
QP
GND
REJ03F0261-0100 Rev.1.00 Jan.10.2008 page 6 of 7
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R8A66160DD/SP
PACKAGE OUTLINE
Product name R8A66160DD R8A66160SP Package 24pin DIP 24pin SOP RENESAS Code PRDP0024AF-A PRSP0024DF-A Previous Code 24P4X-A 24P2X-B
All trademarks and registered trademarks are the property of their respective owners.
REJ03F0261-0100 Rev.1.00 Jan.10.2008 page 7 of 7
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